UCLA electrical engineers develop customizable, energy efficient chip design to maximize data processing

UCLA electrical engineers develop customizable, energy efficient chip design to maximize data processing

As the transistors built into computer chips get smaller and smaller, with billions of them able to fit on a single chip, what happens to excessive power consumption? To solve this problem, the chip makers have decided to rotate the use of transistors, leaving some areas unused at a given time, the so-called “dark silicon”, but which has created its own problem of inefficiency.

Now, UCLA electrical engineers have designed a new type of computer chip that takes advantage of increasingly underutilized processing areas.

The problem of inefficiency in dark silicon areas has emerged over the past decade. Although the transistors continued to shrink, the power consumption of the chip remained the same, causing power outages if all transistors are used at the same time. To stay within the power limit, only transistors in certain areas are “turned on” at any one time. However, areas in use are usually occupied by energy efficient but inflexible hardware accelerator blocks designed to perform an increasing number of coded functions.

Led by Dejan Markovic, a professor of electrical and computer engineering at UCLA Samueli School of Engineering, the team introduced a new, energy-efficient chip design that maximizes areas reserved for data-intensive processing while minimizing areas of dark silicon. Earlier this year, UCLA researchers presented their study to the International Conference on Solid State Circuits of 2022. Theirs was the only article written by a group of university researchers, with industry representatives giving the rest of the presentations.

“The key to our chip’s design is its network of multiple connection layers on the core processing elements. This minimizes delays and maximizes the total area used, “said Dejan Markovic.

“The key to our chip’s design is its network of multiple connection layers on the core processing elements. This minimizes delays and maximizes the total area used, “said Markovic.” Like a network of synchronized traffic lights, the smart grid moves and manages data processing and computing applications efficiently across the entire network. of billions of transistors “.

According to the researchers, the operation of their network is driven by real-time usage statistics along with a switch that monitors which parts of the processing elements are in use, thus maximizing energy efficiency. The design is also reconfigurable, so it can be customized for specific applications.

entitled “An array of 785GMACs / J 784-core 16nm digital signal processors with multilayer switch box interconnect, assembled as a 2 × 2 dielet with 10μm inter-Dielet I / O for multi-program runtimes reconfiguration”, The document is accessible at the IEEE Xplore Library.

Other authors are UCLA graduate students Uneeb Rathore and Sumeet Singh Nagi, as well as Subramanian Iyer, distinguished professor of electrical and computer engineering at UCLA Samueli and holder of the Charles P. Reames Endowed Chair in Electrical Engineering.

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